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d a t a sh eet product speci?cation supersedes data of august 1993 file under integrated circuits, ic02 1996 dec 11 integrated circuits TDA4672 picture signal improvement (psi) circuit with enhanced peaking function
1996 dec 11 2 philips semiconductors product speci?cation picture signal improvement (psi) circuit with enhanced peaking function TDA4672 features luminance signal delay from 20 ns to 1100 ns (minimum step 45 ns) selectable luminance signal peaking with symmetrical overshoots selectable 2.6 or 5 mhz peaking centre frequency and degree of peaking from - 6 db to +9 db in 16 steps of 1 db each selectable noise reduction by coring selectable 5 or 12 v sandcastle input voltage all controls selected via the i 2 c-bus timing pulse generation for clamping and delay time control synchronized by sandcastle pulse automatic luminance signal delay correction using a control loop luminance input signal clamping with coupling capacitor 4.5 to +8.8 v supply voltage minimum of external components. general description the TDA4672 delays the luminance signal. the luminance signal can also be improved by peaking and noise reduction (coring). quick reference data ordering information symbol parameter min. typ. max. unit v p supply voltage (pin 1) 4.5 5 8.8 v i p(tot) total supply current 26 37 46 ma t d(y) y signal delay time 20 - 1130 ns v i(y)(p-p) composite y input signal (peak-to-peak value, pin 16) - 450 640 mv g y voltage gain of y channel -- 1 - db t amb operating ambient temperature 0 - 70 c type number package name description version TDA4672 dip18 plastic dual in-line package; 18 leads (300 mil) sot102-1
1996 dec 11 3 philips semiconductors product speci?cation picture signal improvement (psi) circuit with enhanced peaking function TDA4672 block diagram handbook, full pagewidth med756 black level clamp 180 ns 90 ns 45 ns 90 ns 100 ns black level clamp 450 ns 180 ns control signal 100 nf 13 100 nf 14 3 - (r - y) 7 - (b - y) v ref + 1 - 0.5 5 mhz 2.6 mhz 100 ns 90 ns 5 mhz 2.6 mhz - 0.5 v ref v ref delay time control sandcastle pulse detector black level clamp sandcastle 5 v/12 v cti on/off coring on/off peaking frequency degree of peaking i 2 c-bus receiver 9 10 y delay bk bk, h + v 16 17 i 2 c-bus v ref v ref 100 nf y 8 18 5 n.c. 100 nf 2 sandcastle pulse sda scl coring peaking coring i 2 c-bus i 2 c-bus 100 nf 100 nf 15 v p = 5 to 8 v v ref generation 1 - (r - y) - (b - y) y 11 12 4 6 TDA4672 + + fig.1 block diagram.
1996 dec 11 4 philips semiconductors product speci?cation picture signal improvement (psi) circuit with enhanced peaking function TDA4672 pinning notes 1. pin 3 is connected directly to pin 4. 2. pin 7 is connected directly to pin 6. symbol pin description v p 1 positive supply voltage c dl 2 capacitor of delay time control v i(r - y) 3 (r - y) colour-difference input signal; note 1 v o(r - y) 4 (r - y) colour-difference output signal; note 1 n.c. 5 not connected v o(b - y) 6 (b - y) colour-difference output signal; note 2 v i(b - y) 7 (b - y) colour-difference input signal; note 2 gnd2 8 ground 2 (0 v) sda 9 i 2 c-bus serial data input/output scl 10 i 2 c-bus serial clock input c cor 11 coring capacitor v oy 12 delayed luminance output signal c clp1 13 black level clamping capacitor 1 c clp2 14 black level clamping capacitor 2 c ref 15 capacitor of reference voltage v iy 16 luminance input signal sand 17 sandcastle pulse input gnd1 18 ground 1 (0 v) fig.2 pin configuration. handbook, halfpage TDA4672 med757 1 2 3 4 5 6 7 8 9 18 17 16 15 14 13 12 11 10 v p n.c. c dl gnd2 sda v i(r - y) v o(r - y) v o(b - y) v i(b - y) gnd1 sand v iy v oy c ref c clp2 c clp1 c cor scl
1996 dec 11 5 philips semiconductors product speci?cation picture signal improvement (psi) circuit with enhanced peaking function TDA4672 functional description the TDA4672 contains luminance signal processing. the luminance signal section comprises a variable, integrated luminance delay line with luminance signal peaking and noise reduction by coring. all functions and parameters are controlled via the i 2 c-bus. y-signal path the video and blanking signal is ac-coupled to the input pin 16. its black porch is clamped to a dc reference voltage to ensure the correct operating range of the luminance delay stage. the luminance delay line consists of all-pass filter sections with delay times of 45, 90, 100, 180 and 450 ns (see fig.1). the luminance signal delay is controlled via the i 2 c-bus in steps of 45 ns in the range of 20 to 1100 ns, this ensures that the maximum delay difference between the luminance and colour-difference signals is 22.5 ns. an automatic luminance delay time adjustment in an internal control loop (with the horizontal frequency as a reference) is used to correct changes in the delay time, due to component tolerances. the control loop is automatically enabled between the burst key pulses of lines 16 (330) and 17 (331) during the vertical blanking interval. the control voltage is stored in the capacitor c dl connected to pin 2. the peaking section uses a transversal filter circuit with selectable centre frequencies of 2.6 and 5.0 mhz. it provides selectable degrees of peaking from - 6to+9db and noise reduction by coring, which attenuates the high-frequency noise introduced by peaking. the output buffer stage ensures a low-ohmic video blanking synchronization (vbs) output signal on pin 12 (<160 w ). the gain of the luminance signal path from pin 16 to pin 12 is unity. an oscillation signal of the delay time control loop is present on output pin 12 instead of the vbs signal. it is present during the vertical blanking interval of the burst key pulses in lines 16 (330) to 18 (332). this sync should not be applied for synchronization. colour-difference signal paths the colour-difference input signals (on pins 3 and 7) are connected directly to the output pins. this is for compatibility with other philips semiconductors psi-circuits.
1996 dec 11 6 philips semiconductors product speci?cation picture signal improvement (psi) circuit with enhanced peaking function TDA4672 limiting values in accordance with the absolute maximum rating system (iec 134). gnd1 and gnd2 are connected together. note 1. equivalent to discharging a 200 pf capacitor through a 0 w series resistor. thermal characteristics characteristics v p = 5 v; nominal video amplitude v vb = 315 mv; t h =64 m s; t bk =4 m s (burst key); t amb =25 c and measurements taken in fig.4; unless otherwise speci?ed. symbol parameter conditions min. max. unit v p supply voltage (pin 1) 0 8.8 v v i input voltage (pins 2 to 7 and pins 11 to 16) - 0.1 v p v v 9,10 input voltage at pins 9 and 10 - 0.1 +8.8 v v 17 input voltage at pin 17 - 0.1 +12 v i 8-18 current between pins 8 and 18 - 20 ma i 3-4 current between pins 3 and 4 - 4ma i 6-7 current between pins 6 and 7 - 4ma p tot total power dissipation 0 0.97 w t stg storage temperature - 25 +150 c t amb operating ambient temperature 0 70 c v esd electrostatic handling note 1 for pin 17 - +250 v -- 500 v for other pins - 500 v symbol parameter value unit r th j-a thermal resistance from junction to ambient in free air 82 k/w symbol parameter conditions min. typ. max. unit v p supply voltage (pin 1) 4.5 5 8.8 v i p(tot) total supply current 26 37 46 ma y-signal path v i(y)(p-p) vbs input signal on pin 16 (peak-to-peak value) - 450 640 mv v 16 black level clamping voltage - 3.1 - v i 16 input current during clamping 95 - 190 m a outside clamping -- 0.1 m a r 16 input resistance outside clamping 5 -- m w c 16 input capacitance - 310pf t d(y)(max) maximum y delay time set via i 2 c-bus 1070 1100 1130 ns t d(y)(min) minimum y delay time set via i 2 c-bus - 20 - ns
1996 dec 11 7 philips semiconductors product speci?cation picture signal improvement (psi) circuit with enhanced peaking function TDA4672 d t d(y) minimum delay step set via i 2 c-bus 40 45 50 ns group delay time difference f = 0.5 to 5 mhz; maximum delay - 0 25 ns t d(peak) minimum delay time for peaking 185 215 245 ns g y vbs signal gain measured on output pin 12 (composite signal, peak-to-peak value) v 12 /v 16 ; f = 500 khz; maximum delay - 2 - 10 db i 12 output current (emitter-follower with constant current source) source current - 1 -- ma sink current 0.4 -- ma r 12 output resistance -- 160 w f frequency response for maximum delay f = 0.5 to 3 mhz - 2 - 10 db f = 0.5 to 5 mhz - 4 - 3 - 1db lin signal linearity for a min / a max ; note 1 video contents of 315 mv (p-p) v vbs = 450 mv (p-p) 0.85 --- video contents of 450 mv (p-p) v vbs = 640 mv (p-p) 0.60 --- luminance peaking, selected via i 2 c-bus f peak peaking frequency f c1 ; lcf-bit = 0 4.5 5 5.5 mhz f c2 ; lcf-bit = 1 2.3 2.6 2.9 mhz v peak peaking amplitude for grade of peaking (f c amplitude over 0.5 mhz amplitude) y delay = 215 ns; peaking delay only selectable values from -- 6 - db to - +9 - db each step - 1 - db no limitation of peaking --- % v n(rms) noise voltage on pin 12 (rms value) without peaking; f=0to5mhz -- 1mv cor coring of peaking (coring part referred to 315 mv) cor-bit = 1 - 20 - % symbol parameter conditions min. typ. max. unit
1996 dec 11 8 philips semiconductors product speci?cation picture signal improvement (psi) circuit with enhanced peaking function TDA4672 notes 1. a min : minimum differential voltage gain of the luminance video signal; a max : maximum differential voltage gain of the luminance video signal. 2. a number of more than 31 burst key pulses repeats the counter cycle of delay time control. sandcastle pulse, input voltage selectable via i 2 c-bus v 17 input voltage threshold for h and v sync sc5-bit = 0 (+12 v) 1.1 1.5 1.9 v input voltage threshold for burst sc5-bit = 0 (+12 v) 5.5 6.5 7.5 v input voltage threshold for h and v sync sc5-bit = 1 (+5 v) 1.1 1.5 1.9 v input voltage threshold for burst sc5-bit = 1 (+5 v) 3.0 3.5 4.0 v r 17 input resistance +12 v input level 30 40 50 k w +5 v input level 15 20 25 k w c 17 input capacitance - 48pf t bk burst key pulse width 3.0 4.0 4.6 m s t d leading edge delay for clamping pulse referenced to t bk - 1 -m s n p number of required burst key pulses vertical blanking interval note 2 4 - 31 - i 2 c-bus control, sda and scl v ih high level input voltage on pins 9 and 10 3 - 5v v il low level input voltage on pins 9 and 10 0 - 1.5 v i 9,10 input current on pins 9 and 10 -- 10 m a v o(ack) output voltage at acknowledge on pin 9 i o(ack) =3ma -- 0.4 v i o(ack) output current at acknowledge on pin 9 sink current 3 -- ma symbol parameter conditions min. typ. max. unit
1996 dec 11 9 philips semiconductors product speci?cation picture signal improvement (psi) circuit with enhanced peaking function TDA4672 i 2 c-bus format notes 1. s = start condition. 2. slave address = 1000 100x. 3. ack = acknowledge, generated by the slave. 4. subaddress = subaddress byte, see table 1. 5. data = data byte, see table 1. 6. p = stop condition. 7. x = read/write control bit. x = 0, order to write (the circuit is slave receiver). x = 1, order to read (the circuit is slave transmitter). if more than 1 byte of data is transmitted, then auto-increment of the subaddress is performed. table 1 i 2 c-bus transmission; see table 2 table 2 function of the bits s (1) slave address (2) ack (3) subaddress (4) ack (3) data (5) p (6) function subaddress data d7 d6 d5 d4 d3 d2 d1 d0 y delay/sc 00010000 0 sc5 0 dl4 dl3 dl2 dl1 dl0 peaking and coring 00010001 cor peak lcf 0 pcon3 pcon2 pcon1 pcon0 data function logic 1 logic 0 dl0 set delay in luminance channel 45 ns 0 ns dl1 90 ns 0 ns dl2 180 ns 0 ns dl3 180 ns 0 ns dl4 450 ns 0 ns sc5 select sandcastle pulse voltage +5 v +12 v lcf set peaking frequency response 2.6 mhz 5.0 mhz peak set peaking delay active (190 ns) inactive cor set coring control active inactive pconx set peaking ampli?cation see table 3
1996 dec 11 10 philips semiconductors product speci?cation picture signal improvement (psi) circuit with enhanced peaking function TDA4672 table 3 peaking ampli?cation remarks to the subaddress bytes subaddresses 00h to 0fh are reserved for colour decoders and rgb processors. subaddresses 10 and 11 only are acknowledged. general call address is not acknowledged. power-on reset: d7 to d1 bits of data bytes are set to logic 0, d0 bit is set to logic 1. pcon3 pcon2 pcon1 pcon0 grade of peaking (db) 1111 - 6 1110 - 5 1101 - 4 1100 - 3 1011 - 2 1010 - 1 1001 0 1000 +1 0111 +2 0110 +3 0101 +4 0100 +5 0011 +6 0010 +7 0001 +8 0000 +9
1996 dec 11 11 philips semiconductors product speci?cation picture signal improvement (psi) circuit with enhanced peaking function TDA4672 internal circuitry handbook, full pagewidth med759 + + + + 13 c clp1 + 14 c clp2 15 c ref c cor 11 scl 10 12 y output 9 sda 8 gnd 7 cd input 6 cd output 5 n.c. + 4 cd output 3 cd input 2 1 18 c dl + + + 16 y input 17 sc TDA4672 v p gnd all input and output pins except pins 9, 10 and 17 fig.3 internal circuit.
1996 dec 11 12 philips semiconductors product speci?cation picture signal improvement (psi) circuit with enhanced peaking function TDA4672 test and application information fig.4 test and application circuit. handbook, full pagewidth med758 v p + 5 v v b 18 17 16 15 14 13 12 11 10 n.c. c dl gnd2 sda sda i 2 c-bus 0.1 m f 0.1 m f 15 w TDA4672 v i(r - y) v o(r - y) v o(b - y) v i(b - y) gnd1 sand sandcastle pulse input (vbs) (vbs) v iy v oy c ref c clp2 c clp1 c cor scl 1 2 3 4 5 6 7 8 9 0.1 m f 0.1 m f 0.1 m f 0.1 m f 47 m f
1996 dec 11 13 philips semiconductors product speci?cation picture signal improvement (psi) circuit with enhanced peaking function TDA4672 package outline references outline version european projection issue date iec jedec eiaj sot102-1 93-10-14 95-01-23 unit a max. 12 b 1 (1) (1) (1) b 2 cd e e m z h l mm dimensions (inch dimensions are derived from the original mm dimensions) a min. a max. b max. w m e e 1 1.40 1.14 0.53 0.38 0.32 0.23 21.8 21.4 6.48 6.20 3.9 3.4 0.254 2.54 7.62 8.25 7.80 9.5 8.3 0.85 4.7 0.51 3.7 inches 0.055 0.044 0.021 0.015 0.013 0.009 1.40 1.14 0.055 0.044 0.86 0.84 0.26 0.24 0.15 0.13 0.01 0.10 0.30 0.32 0.31 0.37 0.33 0.033 0.19 0.020 0.15 m h c (e ) 1 m e a l seating plane a 1 w m b 1 b 2 e d a 2 z 18 1 10 9 b e pin 1 index 0 5 10 mm scale note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. dip18: plastic dual in-line package; 18 leads (300 mil) sot102-1
1996 dec 11 14 philips semiconductors product speci?cation picture signal improvement (psi) circuit with enhanced peaking function TDA4672 soldering introduction there is no soldering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. however, wave soldering is not always suitable for surface mounted ics, or for printed-circuits with high population densities. in these situations reflow soldering is often used. this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our ic package databook (order code 9398 652 90011). soldering by dipping or by wave the maximum permissible temperature of the solder is 260 c; solder at this temperature must not be in contact with the joint for more than 5 seconds. the total contact time of successive solder waves must not exceed 5 seconds. the device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (t stg max ). if the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. repairing soldered joints apply a low voltage soldering iron (less than 24 v) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. if the temperature of the soldering iron bit is less than 300 c it may remain in contact for up to 10 seconds. if the bit temperature is between 300 and 400 c, contact may be up to 5 seconds. definitions life support applications these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips for any damages resulting from such improper use or sale. purchase of philips i 2 c components data sheet status objective speci?cation this data sheet contains target or goal speci?cations for product development. preliminary speci?cation this data sheet contains preliminary data; supplementary data may be published later. product speci?cation this data sheet contains ?nal product speci?cations. limiting values limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information where application information is given, it is advisory and does not form part of the speci?cation. purchase of philips i 2 c components conveys a license under the philips i 2 c patent to use the components in the i 2 c system provided the system conforms to the i 2 c specification defined by philips. this specification can be ordered using the code 9398 393 40011.
1996 dec 11 15 philips semiconductors product speci?cation picture signal improvement (psi) circuit with enhanced peaking function TDA4672 notes
internet: http://www.semiconductors.philips.com philips semiconductors C a worldwide company ? philips electronics n.v. 1996 sca52 all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. netherlands: postbus 90050, 5600 pb eindhoven, bldg. vb, tel. +31 40 27 82785, fax. +31 40 27 88399 new zealand: 2 wagener place, c.p.o. box 1041, auckland, tel. +64 9 849 4160, fax. +64 9 849 7811 norway: box 1, manglerud 0612, oslo, tel. +47 22 74 8000, fax. +47 22 74 8341 philippines: philips semiconductors philippines inc., 106 valero st. salcedo village, p.o. box 2108 mcc, makati, metro manila, tel. +63 2 816 6380, fax. +63 2 817 3474 poland: ul. lukiska 10, pl 04-123 warszawa, tel. +48 22 612 2831, fax. +48 22 612 2327 portugal: see spain romania: see italy russia: philips russia, ul. usatcheva 35a, 119048 moscow, tel. +7 095 247 9145, fax. +7 095 247 9144 singapore: lorong 1, toa payoh, singapore 1231, tel. +65 350 2538, fax. +65 251 6500 slovakia: see austria slovenia: see italy south africa: s.a. philips pty ltd., 195-215 main road martindale, 2092 johannesburg, p.o. box 7430 johannesburg 2000, tel. +27 11 470 5911, fax. +27 11 470 5494 south america: rua do rocio 220, 5th floor, suite 51, 04552-903 s?o paulo, s?o paulo - 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